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Senior Principal Design Verification Engineer

Are you interested in quantum imaging? Join us! In this role you can apply your expertise in design verification for ASICs driving our latest sensors – highlighted by their low read noise capabilities. This involves testing digital functions of sensors and validating the products through programming the bring-up systems to achieve world class performance. Your work will enable our cutting-edge imaging products.

We are looking for a senior level digital design verification engineer who has strong proficiency in

  • Design Verification- executing testbench creation, functional coverage, test failures analysis, regression

Because this role involves a combination of collaborative/in-person and independent work, it will take the form of a hybrid work format, with time split between working onsite and remotely.


See education and experience requirements below.

Role Summary

  • Solid understanding of verification methodologies, especially UVM (SystemVerilog (SV)), including:
    • Test planning
    • Test bench creation
    • Code and Functional coverage
    • Directed and random stimulus generation
    • Assertions
    • Regression triage
  • Defining detailed test plan and implementing Verilog simulation test cases to verify design functionality.
  • Build verification environment using SV/UVM methodology
  • Build reusable bus functional models, monitors, checkers and scoreboards
  • Debug product, test and resolve design issues
  • Integration of VIP cores Buses, Controllers, PHYs, etc with other logic within ASIC/FPGA

Required Education, Experience, & Skills:

  • Typically a BS with 10 years of experience or MS with 8 years of experience.
  • Desired majors Electrical Engineering, Computer Engineering, or Computer Science
  • Proficient in SystemVerilog (SV) language for ASIC design, and related FPGA
  • Knowledge of ASIC design flows is highly desirable, and FPGA is a plus
  • Knowledge simulation and verification methodologies (Cadence/Synopsys tool simulator, UVM)
  • Excellent organization and communication skills for interacting between different design groups
  • Proficiency in C/C++ and scripting languages is a plus

Preferred Education, Experience, & Skills

  • BS in EE or Computer Science, MS or Doctoral degree preferred
  • 10+ years of experience in ASIC/FPGA Development (Verilog, System Verilog, UVM